Static random access memory (SRAM) is a type of semiconductor memory that does not need to be refreshed (i.e., it is “static”) because it uses bistable latch circuitry to store each bit. The memory is still “volatile” in the sense that data is eventually lost when the memory is not powered.
SRAMs constitute a significant percentage of the total area for many digital chips as well as the total power consumption. One manner of reducing the leakage power is to reduce the power supply node voltage of the SRAM during a lower power data retention or standby mode. In prior art solutions, a diode connected MOS transistor provides a voltage drop (ΔV), which is around the threshold voltage of the diode connected MOS transistor, from the main power supply voltage during power down mode to provide a lower power supply voltage for the SRAM. However, variations in process and temperature can cause large variations in this voltage drop, which lead to flipping of a cells contents and thus destruction of the stored data. For this reason, a bias controlled device is generally used to ensure a safe data retaining voltage. This approach, however, may maintain the SRAM supply voltage at a level that is too high, and thus does not maximize power savings opportunities.